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HI1396
August 1997
8-Bit, 125 MSPS, Flash A/D Converter
Description
The HI1396 is an 8-bit, ultra high speed flash analog-to-digital converter IC capable of digitizing analog signals at the maximum rate of 125 MSPS. The digital I/O levels of the converter are compatible with ECL 100K/10KH/10K.
Features
* * * * * * * * * * * * Differential Linearity Error 0.5 LSB (Typ) or Less Integral Linearity Error 0.5 LSB (Typ) or Less Built-In Integral Linearity Compensation Circuit Ultra High Speed Operation with Maximum Conversion Rate of 125 MSPS (Min) Low Input Capacitance (Typ) . . . . . . . . . . . . . . . . . 18pF Wide Analog Input Bandwidth (Min for Full Scale Input) . . . . . . . . . . . . . . . . . . 200MHz Single Power Supply . . . . . . . . . . . . . . . . . . . . . . . .-5.2V Low Power Consumption (Typ) . . . . . . . . . . . . .870mW Low Error Rate Operable at 50% Clock Duty Cycle Capable of Driving 50 Loads Direct Replacement for Sony CXA1396
Ordering Information
PART NUMBER HI1396JCJ HI1396AIL TEMP. RANGE (oC) -20 to 75 -20 to 100 PACKAGE 42 Ld SBDIP 68 Ld CLCC PKG. NO. D42.6 J68.A
Applications
* Video Digitizing * Communication Systems * HDTV (High Definition TV) * Radar Systems * Direct RF Down-Conversion * Digital Oscilloscopes
Pinouts
HI1396 (SBDIP) TOP VIEW
NC NC AVEE NC LINV DVEE DGND1 DGND2 (LSB) D0 D1 D2 1 2 3 4 5 6 7 8 9 42 NC 41 VRT 40 NC 39 AVEE 38 AVEE 37 NC 36 NC 35 AGND 34 VIN 33 AGND 32 VRM 31 AGND 30 VIN 29 AGND 28 NC 27 NC 26 AVEE 25 AVEE 24 NC 23 VRB 22 NC NC AVEE AVEE NC VRT NC AVEE NC NC NC LINV NC DVEE NC DGND1 DGND2 NC
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
HI1396 (CLCC) TOP VIEW
NC NC NC AGND VIN AGND VRM AGND VIN AGND NC NC NC NC NC
60 NC 59 AVEE 58 AVEE 57 NC 56 VRB 55 NC 54 NC 53 NC 52 CLK 51 CLK 50 NC 49 MINV 48 NC 47 DVEE 46 NC 45 NC 44 NC
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
D3 10 D4 11 D5 12 D6 13 (MSB) D7 14 DGND2 15 DGND2 16 DVEE 17 MINV 18 NC 19 CLK 20 CLK 21
NC NC (LSB) D0 D1 D2 D3 D4 D5 D6
(MSB) D7 NC DGND2 DGND1 NC
NC NC
NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
File Number
3576.3
4-1156
HI1396 Functional Block Diagram
MINV R1 VRT R/2 R 1 R D7 (MSB) 2 R D6 COMPARATOR
63 R VIN 64 R 65 OUTPUT D3 R 126 R R2 VRM R 128 R D0 (LSB) 129 127 ENCODE LOGIC D1 D2 D4 D5
R 191 R VIN 192 R 193
R 254 R 255 VRB CLK CLK R3 R/2
CLOCK DRIVER
LINV
4-1157
HI1396
Absolute Maximum Ratings TA = 25oC
Supply Voltage (AVEE , DVEE) . . . . . . . . . . . . . . . . . . . . . . . . . . .-7V Analog Input Voltage (VIN) . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V Reference Input Voltage VRT , VRB , VRM . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.7V to +0.5V |VRT - VRB | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5V Digital Input Voltage CLK, CLK, MINV, LINV . . . . . . . . . . . . . . . . . . . . . . . -4V to +0.5V |CLK-CLK | . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V VRM Pin Input Current (IVRM) . . . . . . . . . . . . . . . . . . -3mA to +3mA Digital Output Current (ID0 to ID7) . . . . . . . . . . . . . . . -30mA to 0mA
Thermal Information
Thermal Resistance (Typical, Note 1) JAoC/W JCoC/W SBDIP Package . . . . . . . . . . . . . . . . . . 45 7 CLCC Package . . . . . . . . . . . . . . . . . . 45 8 Maximum Junction Temperature Ceramic Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175oC Maximum Storage Temperature Range (TSTG) . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions (Note 1)
Temperature Ranges (Note 4) SBDIP Package, TA . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 75oC CLCC Package, TC . . . . . . . . . . . . . . . . . . . . . . . . -20oC to 100oC Supply Voltage Ranges AVEE , DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -5.5V to -4.95V AVEE - DVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V AGND - DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.05V to 0.05V Reference Input Voltage VRT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.1V to 0.1V VRB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.2V to -1.8V Analog Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . VRB to VRT Pulse Width of Clock tPW1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns (Min) tPW0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.0ns (Min)
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER SYSTEM PERFORMANCE Resolution Integral Linearity Error, INL HI1396JCJ, HI1396AIL Differential Linearity Error, DNL HI1396JCJ, HI1396AIL ANALOG INPUT Input Bandwidth Analog Input Capacitance, CIN Analog Input Resistance, RIN Input Bias Current, IIN REFERENCE INPUTS Reference Resistance, RREF Offset Voltage EOT EOB DIGITAL INPUTS Logic H Level, VIH Logic L Level, VIL Logic H Current, IIH Logic L Current, IIL Input Capacitance DIGITAL OUTPUTS Logic H Level, VOH Logic L Level, VOL
TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) TEST CONDITIONS MIN TYP MAX UNIT
fC = 125 MSPS fC = 125 MSPS VIN = 2VP-P VIN = 1V + 0.07VRMS VIN = -1V -
8 0.3 -
0.5 0.5 400
Bits LSB LSB
200 50 20
17 190 130
MHz pF k A mV mV
75 VRT VRB 8 0
110 19 15
155 32 24
-1.13 Input Connected to -0.8V Input Connected to -1.6V 0 0 -
7
-1.50 50 50 -
V V A A pF
RL = 50 to -2V RL = 50 to -2V
-1.10 -
-
-1.62
V V
4-1158
HI1396
Electrical Specifications
PARAMETER TIMING CHARACTERISTICS Output Rise Time, tr Output Fall Time, tf Output Delay, tOD H Pulse Width of Clock, tPW1 L Pulse Width of Clock, tPW0 DYNAMIC CHARACTERISTICS Maximum Conversion Rate, fC Aperture Jitter, tAJ Sampling Delay, tDS Signal to Noise Ratio (SINAD) RMS Signal = ----------------------------------------------------------------RMS Noise + Distor tion Error Rate Differential Gain Error, DG Differential Phase Error, DP POWER SUPPLY CHARACTERISTICS Supply Current, IEE Power Consumption NOTES: 1. Electrical Specifications guaranteed within stated operating conditions. 2. TPS: Times Per Sample. 3. ( V RT - V RB ) P D = I EE * V EE + -----------------------------------R
REF 2
TA = 25oC, AVEE = DVEE = -5.2V, VRT = 0V, VRB = -2V (Note 1) (Continued) TEST CONDITIONS MIN TYP MAX UNIT
RL = 50 to -2V, 20% to 80% RL = 50 to -2V, 20% to 80%
0.5 0.5 3.0 4.0 4.0
0.9 1.0 3.6 -
1.2 1.3 4.2 -
ns ns ns ns ns
Error Rate 10-9 TPS (Note 2)
125 -
10 1.5 46 40 1.0 0.5
10-9 -
MSPS ps ns dB dB TPS (Note 2) % Degree
Input = 1MHz, Full Scale fC = 125 MSPS Input = 31.5MHz, Full Scale fC = 125 MSPS Input = 31.249MHz, Full Scale Error > 16 LSB, fC = 125 MSPS NTSC 40 IRE Mod. Ramp, fC = 125 MSPS
-
-230 Note 3 -
-160 870
-
mA mW
4. TA specified in still air and without heat sink. To extend temperature range, appropriate heat management techniques must be employed.
Timing Diagram
N+1
ANALOG IN
N
N+2 tPW1 CLK CLK tPW0
DIGITAL OUT tOD
N-1
20%
80%
N
20%
N+1 80% tf
tr
FIGURE 1.
4-1159
HI1396 Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 29, 31, 33, 35 LCC 49, 51, 53, 55 SYMBOL AGND I/O STANDARD VOLTAGE LEVEL 0V
EQUIVALENT CIRCUIT
DESCRIPTION Analog GND. Used as GND for input buffers and latches of comparators. Isolated from DGND1, DGND2. Analog VEE -5.2V (Typ). Internally connected to DVEE (Resistance: 4 to 6). Bypass with 0.1F to AGND.
1, 25, 26, 38, 39
41, 42, 62, 63, 67
AVEE
-
-5.2V
21 20
35 34
CLK CLK
I
ECL
DGND1
CLK Input. Input complementary to CLK. When left open pulled down to -1.3V. Device is operable without CLK input, but use of complementary inputs of CLK and CLK is recommended to obtain stable high speed operation.
R R CLK CLK R
R
DVEE
R
R
5, 16 6, 15 4, 17
7, 24 8, 23 5, 30
DGND1 DGND2 DVEE
-
0V 0V -5.2V
Digital GND for internal circuits. Digital GND for output transistors. Digital VEE . Internally connected to AVEE (resistance: 4 to 6). Bypass with 0.1F to DGND
DGND2
7
14
D0
O
ECL
LSB of data outputs. External pull-down resistor is required. Data outputs. External pull-down resistors are required.
8 9 10 11 12 13 14
15 16 17 18 19 20 21
D1 D2 D3 D4 D5 D6 D7
DVEE DI
MSB of data outputs. External pull-down resistor is required.
4-1160
HI1396 Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 3 LCC 3 SYMBOL LINV I/O I STANDARD VOLTAGE LEVEL ECL
DGND1
(Continued)
EQUIVALENT CIRCUIT
DESCRIPTION Input pin for D0 (LSB) to D6 output polarity inversion (see A/D Output Code Table). Pulled low when left open.
18
32
MINV
I
ECL
R R LINV OR MINV R -1.3V
Input pin for D7 (MSB) output polarity inversion (see A/D Output Code Table). Pulled low when left open.
DVEE
R
30, 34
50, 54
VIN
I
VRT to VRB
AGND
Analog input pins. These two pins must be connected externally, since they are not internally connected.
VIN VIN
AVEE
23
39
VRB
I
-2V
VRT
R1 R/2
Reference voltage (bottom). Typically -2V. Bypass with a 0.1F and 10F to AGND.
R COMPARATOR 1 R COMPARATOR 2 R
32 41
52 65
VRM VRT
I I
VRB/2 0V
Reference voltage mid point. Can be used as a pin for integral linearity compensation. Reference voltage (top) typically 0V. When a voltage different from AGND is applied to this pin, bypass with a 0.1F and 10F to AGND.
VRM
R2 R
COMPARATOR 127 COMPARATOR 128 R COMPARATOR 129 R COMPARATOR 130
R COMPARATOR 255 VRB R3 R/2
4-1161
HI1396 Pin Descriptions and I/O Pin Equivalent Circuits
PIN NUMBER DIP 2, 19, 22, 24, 27, 28, 36, 37, 40, 42 LCC 1, 2, 4, 6, 9-13, 25-29, 31, 33, 36-38, 40, 43-48, 56-61, 64, 66, 68 SYMBOL NC I/O STANDARD VOLTAGE LEVEL (Continued)
EQUIVALENT CIRCUIT
DESCRIPTION Unused pins. No internal connections have been made to these pins. Connecting them to AGND or DGND on PC board is recommended.
A/D OUTPUT CODE TABLE MINV 1, LINV 1 VIN (Note 5) 0V 0 1 STEP D7 D0 D7 0, 1 D0 D7 1, 0 D0 D7 0, 0 D0
000 * * * * * 00 000 * * * * * 00 000 * * * * * 01 * * *
100 * * * * * 00 100 * * * * * 00 100 * * * * * 01 * * * 111 * * * * * 11 000 * * * * * 00 * * * 011 * * * * * 10 011 * * * * * 11 011 * * * * * 11
011 * * * * * 11 011 * * * * * 11 011 * * * * * 10 * * * 000 * * * * * 00 111 * * * * * 11 * * * 100 * * * * * 01 100 * * * * * 00 100 * * * * * 00
111 * * * * * 11 111 * * * * * 11 111 * * * * * 10 * * * 100 * * * * * 00 011 * * * * * 11 * * * 000 * * * * * 01 000 * * * * * 00 000 * * * * * 00
-1V
127 128
011 * * * * * 11 100 * * * * * 00 * * *
254 255 -2V NOTE: 5. VRT = 0V, VRB = -2V.
111 * * * * * 10 111 * * * * * 11 111 * * * * * 11
Test Circuits
SIGNAL SOURCE fCLK 4 -1kHz + ECL LATCH VIN 8 HI1396 CLK CLK ECL LATCH A B COMPARATOR A>B PULSE COUNTER
2VP-P SINEWAVE DATA 16 SIGNAL SOURCE fCLK fCLK/4
FIGURE 2. MAXIMUM CONVERSION RATE TEST CIRCUIT
4-1162
HI1396 Test Circuits
(Continued)
HI20201 VIN AMP DUT HI1396 CLK 8 ECL LATCH 8 10 BIT D/A
CLK NTSC SIGNAL SOURCE
SG (CW) 50 VBB
DELAY
VECTOR SCOPE DG/DP
FIGURE 3. DIFFERENTIAL GAIN AND PHASE ERROR TEST CIRCUIT
+V
S2
+ S1
S1 : A < B : ON S2 : A > B : ON
-V AB 8 COMPARATOR A8 A1 A0 B8 B1 B0 BUFFER
"0" DVM CLK (125 MSPS)
"1" 8 00000000 TO 11111110
CONTROLLER
FIGURE 4. INTEGRAL AND DIFFERENTIAL LINEARITY ERROR TEST CIRCUIT
4-1163
HI1396 Test Circuits
(Continued)
IIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 HI1396JCJ 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 A IEE A IEE -5.2V -5.2V -2V 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 -1V A
-1V
-2V A IIN 61 62 63 64 65 66 67 68 1 2 3 4 5 6 7 8 9 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
HI1396AIL
FIGURE 5A.
FIGURE 5B.
FIGURE 5. ANALOG INPUT BIAS AND POWER SUPPLY CURRENT TEST CIRCUITS
VIN 67.5MHz AMP 0V -1V -2V
: VARIABLE
VIN fR CLK OSC2 67.5MHz ECL BUFFER HI1396 8 LOGIC ANALYZER
OSC1
CLK
t VIN
t
1024 SAMPLES
129 128 127 126 125
(LSB)
CLK
APERTURE JITTER
Aperture jitter is defined as follows: 256 t AJ = ------ = --------- x 2f 2 t Where (unit: LSB) is the deviation of the output codes when the input frequency is exactly the same as the clock and is sampled at the largest slew rate point. FIGURE 6A. FIGURE 6B. APERTURE JITTER TEST METHOD
FIGURE 6. SAMPLING DELAY AND APERTURE JITTER TEST CIRCUIT
4-1164
HI1396
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. Taiwan Limited 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
4-1165

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